ADVANCE PROGRAM
 
                                     AND

                             CALL FOR PARTICIPATION


                          3rd International Workshop on
                    Algorithms and Parallel VLSI Architectures

                              August 29-31, 1994 
                               Leuven - Belgium

 

This third workshop on Algorithms and Parallel VLSI Architectures addresses
novel research in the area of highly parallel systems, focused on algorithms,
architectures as well as design methodologies and compilation.  Both custom
realisation and programmable processor realisation are included.

It is a continuation of two previous workshops of the same name which
were held in Pont-a-Mousson, France, June 1990, and Bonas, France,
June 1991.
 
The Workshop will be held in the Arenberg Castle of the Katholieke
Universiteit Leuven. Leuven is located in the centre of Belgium, only
30 km from Brussels and 20 km from Brussels International Airport.

  
                           CONFERENCE COMMITTEE 


Chairmen:   Marc Moonen       Katholieke Universiteit Leuven, Belgium
            Francky Catthoor  IMEC, Belgium

Members:    Ed Deprettere     Delft University of Technology, The Netherlands
            Patrick Dewilde   Delft University of Technology, The Netherlands
            Patrice Quinton   INRIA/IRISA, France
            Yves Robert       ENS Lyon, France
            Lothar Thiele     Universitat des Saarlandes
            Joos Vandewalle   Katholieke Universiteit Leuven, Belgium


                                 SPONSORS

The workshop is partly sponsored by the EC (BRA project 6632), the
European Association for Signal Processing (EURASIP), and the Belgian
National Fund for Scientific Research (NFWO), and is organized in
cooperation with the IEEE Benelux Signal Processing Chapter, the IEEE
Benelux Circuits and Systems Chapter, and INRIA, France.


                             TECHNICAL PROGRAM 

The technical program includes 1 hour invited papers, as well as
contributed papers, presented in regular presentation sessions (20
mins per paper) and short presentation sessions (10 mins per paper).
For all contributed papers, additional poster sessions will be organized.


       Parallel Algorithms :
            linear and multilinear algebra, filtering and transforms,
            for sonar and radar, digital audio, image and video,
            communications, computer graphics, automatic control

            Keynote Speaker:  P.A. Regalia   ENST, France

       Parallel Architectures :
            arrays, programmable SIMD and MIMD architectures

            Keynote Speaker:  K. Vissers     Philips, The Netherlands

       Parallel Compilation :
            design methodologies, automated architecture synthesis,
            parallelisation techniques

            Keynote Speaker:  P. Feautrier   PriSM-CNRS, France


                          GENERAL INFORMATION

The full advance program, registration form and hotel booking form are
available via anonymous ftp.

   ftp address: gate.esat.kuleuven.ac.be (134.58.56.20)                     
   directory:   /pub/SISTA/publications
   files:       palgar_registration.Z     (compressed ascii)  
                palgar_registration.ps.Z  (compressed PostScript)

For further information, contact the workshop secretariat:

             Filiep Vanpoucke
             Department of Electrical Engineering - ESAT
             Katholieke Universiteit Leuven
             K. Mercierlaan 94, B-3001 Heverlee, Belgium
             tel: +32 16 220931, fax: +32 16 221855
             e-mail: filiep.vanpoucke@esat.kuleuven.ac.be